IC Layout Design Engineer
Responsibilities
- Perform custom IC layout using Cadence software
- Duties include cell layout, layout verification, and all similar layout design functions
- Responsible for layout verification, debugging and layout optimization
Requirement
- Diploma or above in Electronics or above with good academic result in circuit theories
- Fresh graduates are welcomed
- Knowledge in CMOS IC layout
- Knowledge in CMOS device, fabrication process and electronic theories
- Able to read circuit schematics independently
- Some basic IC design knowledge would be a plus
- Some basic knowledge in special analog layout skill such as ESD, Latch-up, matching would be a plus
- Training will be provided to suitable candidates
We offer attractive compensation package (including 5-day work, medical and dental insurance) to the right candidates. Interested parties please email your full CV with RECENT and EXPECTED salary to HR Department through jobs@appotech.com (All personal data collected will be used for recruitment related purpose only).